【專題演講】Analog Design Challenges and Strategies when Migrating from Planar to FinFET

▌主講人：聯發科技 溫松翰資深技術經理

▌日期：2025年5月23日(五)上午10:30-11:30

▌地點：國立臺灣大學學新館2樓Space M

★報名連結：https://reurl.cc/rEYR61

‧Abstractl：

High-performance computation has enabled many killer applications that have significantly changed our life, such as ChatGPT and autonomous driving. The key driving force behind this comes from the processing scaling and FinFET devices. In this talk, I’d like to invite you together to review the history of the processing scaling and understand the reason why we need to immigrate from 2D planer devices to 3D FinFETs, and corresponding benefits we might gain and of course, the trade-offs we might compromise with. This brings lots of design challenges for designers, especially for analog and mixed-signal design, in not only circuit design, but also device modeling, simulation tools and layout complexities…etc. Therefore, I’ll be also sharing some practical strategies and my opinions for these limitations. At last, I’d like to talk about my observations for ISSCC FinFET papers during 2020-2025 and share you which research topics you could pay attention to.

‧Speaker Bio：

Shon-Hang Wen received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2005 and 2007, respectively. In 2008, he joined MediaTek Inc., Hsinchu, Taiwan, where he is currently a senior department manager. During 2021-2024, he also served as an ITPC of ISSCC analog subcommittee. His research interests include audio and precision data converters, headphone and speaker amplifiers, microphone interfaces, envelope tracking modulator, and power management unit as well, which are used in VoIP, cellular, Bluetooth and wireless connectivity products. He holds 30+ U.S. patents and has authored or coauthored 12 journal and conference papers.

‧主辦單位：教育部先進製程IC設計人才培育計畫

‧協辦單位：聯發科技-臺大創新研究中心、臺大電子工程學研究所

‧指導單位：教育部